asahi kasei [akd4641en-a] 2006/03 - 1 - general description the akd4641 is an evaluation board for the ak4641, 16bit stereo codec with built-in microphone-amplifier and 16bit mono codec for bluetooth interface. the akd4641 can evaluate a/d converter and d/a converter separately in addition to loopback mode (a/d d/a). the akd4641 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. ? ordering guide akd4641en -a --- evaluation board for AK4641EN (cable for connecting with printer port of ibm-at, compatible pc and control software are packed with this. this control software does not support windows nt.) function ? dit/dir with optical input/output ? bnc connector for an external clock input ? 10pin header for i 2 c control mode ? on board headphone-amp (max4410) and speaker-amp (lm4889) agnd auxin+ clock gen ak4641 dvdd avdd mout2 5v regulator bvdd mic jack auxin- mout+/- lout rout audio i/f bluetooth i/f 10pin header 10pin header control data 10pin header dir ak4114 3.3v mout+ mout- mout hp jack hp-amp max4410 spk-amp lm4889 opt in opt out figure 1. akd4641 block diagram * circuit diagram and pcb layout are attached at the end of this manual evaluation board rev.1 for AK4641EN a kd4641en- a
asahi kasei [akd4641en-a] 2006/03 - 2 - evaluation board manual ? operation sequence 1) set up the power supply lines. 1-1) when avdd, bvdd, dvdd and vcc are supplied from the regulator. (avdd, bvdd, dvdd and vcc jack should be open.). see ? other jumper pins set up (page 9)?. [reg] (red) = 5v [avdd] (orange) = open : 3.3v is supplied to avdd of ak4641 from regulator. [bvdd] (orange) = open : 3.3v is supplied to bvdd of ak4641 from regulator. [dvdd] (orange) = open : 3.3v is supplied to dvdd of ak4641 from regulator. [vcc] (orange) = open : 3.3v is supplied to logic block from regulator. [h/svdd] (orange) = 3.3v : for max4410 and lm4889 logic (typ.3.3v) [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground 1-2) when avdd, bvdd, dvdd and vcc are not supplied from the regulator. (avdd, bvdd, dvdd and vcc jack should be open). see ? other jumper pins set up (page 9)?. [reg] (red) = ?reg? jack should be open. [avdd] (orange) = 2.6 3.6v : for avdd of ak4641 (typ. 3.3v) [bvdd] (orange) = 2.6 3.6v : for bvdd of ak4641 (typ. 3.3v) [dvdd] (orange) = 2.6 3.6v : for dvdd of ak4641 (typ. 3.3v) [vcc] (orange) = 2.6 3.6v : for logic (typ. 3.3v) [h/svdd] (orange) = 2.6 3.6v : for max4410 and lm4889 logic (typ.3.3v) [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground each supply line should be distributed from the power supply unit. dvdd and vcc must be same voltage level. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the ak4641 and ak4114 should be reset once bringing sw1, 2 ?l? upon power-up. ? evaluation mode 1. evaluation of 16bit stereo codec in case of ak4641 evaluation using ak4114, it is ne cessary to correspond to audio interface format for ak4641 and ak4114. about ak4641?s audio interface format, refer to datasheet of ak4641. about ak4114?s audio interface format, refer to table 2 in this manual. (1-1) evaluation of recording block (mic, adc) using dit of ak4114 (1-2) evaluation of playback block (hp, spk, mout) using dir of ak4114 (1-3) evaluation of loop back (adc dac) using 16bit mono codec (1-4) all interface signals including master clock are fed externally.
asahi kasei [akd4641en-a] 2006/03 - 3 - (1-1) evaluation of recording block (mic, adc) using dit of ak4114 port2 (dit) and x2 (x?tal) are used. dit generates audio bi-phase signal from received data and which is output through optical connector (totx141). nothing should be connected to port1 (dir) and port3 (audio i/f), j12 (ext). jp25 (ext) is short. cm0 is se t ?h ? and cm1 is set ?l ? for sw1, ak4114 is set x?tal mode. jp26 bick2 jp24 xti jp27 bick1 jp28 bick_inv thr mclk_sel port dir mcko02 mcko01 jp30 inv port dir jp32 sdti1 jp31 lrck2 jp33 sdti2 jp29 lrck1 por t dir port dir loop dir dit does not operate under fs = 32khz, this mode corresponds to fs = 32khz and over. (1-2) evaluation of playback block (hp, spk, mout) using dir of ak4114 port1 (dir) is used. nothing should be connected to port3 (audio i/f) and j12 (ext). x1 (x?tal) is removed. jp25 (ext) is short. cm0 is set ?l ? and cm1 is set ?l ? for sw1, ak4114 is set pll mode. jp26 bick2 jp24 xti jp27 bick1 jp28 bick_inv thr mclk_sel port dir mcko02 mcko01 jp30 inv port dir jp32 sdti1 jp31 lrck2 jp33 sdti2 jp29 lrck1 por t dir port dir loop dir dir does not operate under fs = 32khz, this mode corresponds to fs = 32khz and over.
asahi kasei [akd4641en-a] 2006/03 - 4 - (1-3) evaluation of loop back (adc dac) using 16bit mono codec x2 (x?tal) is used. nothing should be connected to port1 (dir), port2 (dit) and port3 (audio i/f). jp26 bick2 jp24 xti jp27 bick1 jp28 bick_inv thr mclk_sel port dir mcko02 mcko01 jp30 inv port dir jp32 sdti1 jp31 lrck2 jp33 sdti2 jp29 lrck1 por t dir port dir loop dir (1-4) all interface signals including master clock are fed externally. port3 (audio i/f) and j12 (ext) is used. nothing should be connected to port1 (dir). x2 (x?tal) is removed. jp25 (ext) and r51 should be properly selected in order to much the output impedance of the clock generator. jp26 bick2 jp24 xti jp27 bick1 jp28 bick_inv thr mclk_sel port dir mcko02 mcko01 jp30 inv port dir jp32 sdti1 jp31 lrck2 jp33 sdti2 jp29 lrck1 por t dir port dir loop dir jp28 (bick_inv) is jumper which decides polarity of bick, set ?thr? or ?inv? for audio interface format.
asahi kasei [akd4641en-a] 2006/03 - 5 - 2. evaluation of 16bit mono codec (2-1) set up jumper pins of bbick clock (2-2) set up jumper pins of bsync clock (2-3) set up jumper pins of two types of data formats (2-4) evaluation of adc (auxin) using 16bit mono codec (2-5) evaluation of dac (mout) using 16bit mono codec (2-6) evaluation of loop back (adc dac) using 16bit mono codec (2-1) set up jumper pins of bbick clock input frequency of bbick can be set up in turn ?32fs?,?64fs? or ?128fs? from left. (2-2) set up jumper pins of bsync clock input frequency of bsync can be set up in turn ?2fs? or ?1fs? from left. when an external clock through a bnc connector (j10: bbick and j11: bsync) is supplied, select ext on jp18 (bbick_sel) and jp20 (bsync_sel) and short jp17 (xte). jp22 (ext1) and jp23 (ext2) and r44 and r45 should be properly selected in order to much the output impedance of the clock generator. (2-3) set up jumper pins of two types of data formats (2-3-1) set up jumper pins of ?i2s? (2-3-2) set up jumper pins of ?short format sync? bbick_sel jp18 ext 32fs 64fs 128fs bbick_sel jp18 ext 32fs 64fs 128fs bbick_sel jp18 ext 32fs 64fs 128fs bsync_sel1 jp20 ext 1fs 2fs bsync_sel1 jp20 ext 1fs 2fs bsync_sel2 jp21 i2s short jp39 thr inv bbick_inv bsync_sel2 jp21 i2s short jp39 thr inv bbick_inv
asahi kasei [akd4641en-a] 2006/03 - 6 - (2-3-3) set up jumper pins of ?msb justified? (2-4) evaluation of adc (auxin) using 16bit mono codec port5 (bth i/f) and x1 (x?tal) are used. nothing should be connected to j10 (bbick) and j11 (bsync). jp19 bbick2 jp17 xte bbick1 clk_sel por t int ext clk jp35 por t int jp38 jp37 sdti jp36 bsync2 jp40 bsync1 por t int port int loop port (2-5) evaluation of dac (mout) using 16bit mono codec port5 (bth i/f) and x1 (x?tal) are used. nothing should be connected to j10 (bbick) and j11 (bsync). when an bsync through a port5 connector (bth i/f) is supplied, open jp20 (bsync_sel). jp19 bbick2 jp17 xte bbick1 clk_sel por t int ext clk jp35 por t int jp38 jp37 sdti jp36 bsync2 jp40 bsync1 por t int port int loop port bsync_sel2 jp21 i2s short jp39 thr inv bbick_inv
asahi kasei [akd4641en-a] 2006/03 - 7 - (2-6) evaluation of loop back (adc dac) using 16bit mono codec x1 (x?tal) are used. nothing should be connected to port5 ( bth -i/f ), j10 (bbick) and j11 (bsync). jp19 bbick2 jp17 xte bbick1 clk_sel por t int ext clk jp35 por t int jp38 jp37 sdti jp36 bsync2 jp40 bsync1 port int port int loop port
asahi kasei [akd4641en-a] 2006/03 - 8 - ? dip switch set up [sw1] : mode setting of ak4114 on is ?h?, off is ?l?. no. name on (?h?) off (?l?) default 1 dif0 on 2 dif2 ak4114 audio format setting see table 2 on 3 cm0 off 4 cm1 ak4114 auto (x?tal / pll) mode on 5 ocks1 off 6 tst2 off 7 nc fixed to ?l? off table 1. mode setting for ak4534 and ak4114 mode dif2 dif0 ak4114 daux ak4114 sdto 0 0 0 24bit, msb justified 16bit, lsb justified 1 0 1 24bit, msb justified 24bit, lsb justified 2 1 0 24bit, msb justified 24bit, msb justified 3 1 1 24bit, i 2 s 24bit, i 2 s table 2. setting for ak4114 audio interface format mode cm1 cm0 unlock pll x'tal clock source sdto 0 0 0 - on on(note) pll rx 1 0 1 - off on x'tal daux 0 on on pll rx 2 1 0 1 on on x'tal daux 3 1 1 - on on x'tal daux on: oscillation (power-up), off: stop (power-down) note : when the x?tal is not used as clock comparison for fs detection (i.e. xtl1,0= ?1,1?), the x?tal is off. table 3. clock operation mode select no. ocks1 mcko1 mcko2 x?tal fs (max) 0 0 256fs 256fs 256fs 96 khz 2 1 512fs 256fs 512fs 48 khz table 4. master clock frequency select (stereo mode)
asahi kasei [akd4641en-a] 2006/03 - 9 - ? other jumper pins set up 1. jp1 (gnd): analog ground and digital ground open : separated. short : common. (the connector ?dgnd? can be open.) 2. jp3 (avdd_sel): avdd of the ak4641 reg : avdd is supplied from the regulator (?avdd? jack should be open). < default > avdd : avdd is supplied from ?avdd ? jack. 3. jp4 (bvdd_sel): bvdd of the ak4641 avdd : avdd is supplied from ?avdd?. < default > bvdd : bvdd is supplied from ?bvdd ? jack. 4. jp5 (dvdd_sel): bvdd of the ak4641 bvdd : dvdd is supplied from ?bvdd?. < default > dvdd : bvdd is supplied from ?bvdd ? jack. 5. jp2 (d3.3v_sel): vcc of logic dvdd : vcc is supplied from ?dvdd?. < default > vcc : vcc is supplied from ?vcc ? jack. 6. jp6 (lout/hp_sel): select analog signal of lout pin lout : analog signal of lout pin is output from j1 (rca) connector. < default > rout : analog signal of lout pin is output from j2 (mini jack) connector. 7. jp7 (rout/hp_sel): select analog signal of rout pin lout : analog signal of lout pin is output from j1 (rca) connector. < default > rout : analog signal of lout pin is output from j2 (mini jack) connector. 8. jp8 (shdn_l): left-channel shutdown mode for max4410 open : left-channel active mode. short : left-channel shutdown mode. < default > 9. jp9 (shdn_r): right-channel shutdown mode for max4410 open : right-channel active mode. short : right-channel shutdown mode. < default > 10. jp12 (mout2/spk_sel): select analog signal of mout2 pin mout2 : analog signal of mout2 pin is output from j7 (rca) connector. < default > spk : analog signal of mout2 pin is output from speaker. 11. jp15 (shdn_spk): shutdown mode for lm4889 open : speaker active mode. short : speaker shutdown mode. < default > 12. jp34 (bsdto): please make use of open < default >
asahi kasei [akd4641en-a] 2006/03 - 10 - ? the function of the toggle sw upper-side is ?h? and lower-side is ?l?. [sw1] (dir): power down of the ak4114. keep ?h? during normal operation. keep ?l? when the ak4114 is not used. [sw2] (pdn): power down of the ak4641. keep ?h? during normal operation. ? indication for led [led1] (erf): monitor int0 pin of the ak4114. led turns on when the ak4114 has some error. ? i 2 c- bus control interface the ak4641 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port4 (ctrl) with pc by 10 wire flat cable packed with the akd4641. connect csn scl sda 10pin header 10pin connector 10 wire flat cable pc akd4641 figure 2. connect of 10 wire flat cable
asahi kasei [akd4641en-a] 2006/03 - 11 - ? analog input / output circuits 1. input circuits 1-1. mic input circuit figure 3. mic input circuit (1) analog signal is input to int pin via j4 connector. jp11 mic ext int (2) analog signal is input to ext pin via j4 connector. jp11 mic ext int 1-2. auxin+ / auxin- input circuit figure 4. auxin+ / auxin- input circuits ext ext j4 mic int int jp11 mic rca + c29 1u r29 47k j5 auxin+ auxin+ r30 47k + c27 1u j6 auxin- auxin- rca
asahi kasei [akd4641en-a] 2006/03 - 12 - 2. output circuits 2-1. lout / rout output circuit figure 5. lout /rout output circuit 2-2. mout2 output figure 6. mout2 output circuit hp lout for hpr-amp jp7 rout/hp_sel r28 10k lout for hpl-amp jp6 lout/hp_sel r20 10k rout + c23 22u r27 220 j3 rout r19 220 j1 lout rca rca rout + c21 22u hp f or spk-amp j7 mout2 jp12 mout2/spk_sel mout2 + c30 22u r32 10k rca spk mout2 r31 220
asahi kasei [akd4641en-a] 2006/03 - 13 - 2-3. mout+/ ? output circuit figure 7. mout+/ ? output circuit (1) signal of mout+ pins are output from j8. (2) signal of mout ? pins are output from j8. (3) signal of mout+ / - pins are output from j9. ? akm assumes no responsibility for the trouble when using the above circuit examples. + c31 22u jp14 diff1 r35 10k r39 10k r33 220 j9 mout 2 3 1 23 1 + c34 22u r42 10k rca j8 mout+ r41 100 jp13 mout+/-_sel mout+ mout+ mout- jp16 diff2 r40 100 mout- mout+/-_sel jp13 mout+ mout- diff1 jp14 diff2 jp16 mout+/-_sel jp13 mout+ mout- diff1 jp14 diff2 jp16 mout+/-_sel jp13 mout+ mout- diff1 jp14 diff2 jp16
asahi kasei [akd4641en-a] 2006/03 - 14 - control software manual ? set-up of evaluation board and control software this evaluation board supports to i 2 c control. 1. set up the akd4641 according to previous term. 2. connect ibm-at compatible pc with akd4641 by 10-line type flat cable (packed with akd4641). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?ak4641 evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4641.exe? to set up the control program. 5. then please evaluate according to the follows. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port setup? button. 3. click ?write default? button. 4. then set up the dialog and input data. ? explanation of each buttons 1. [port reset] : set up the port. when this is pushed , the printer port or usb port is selected automatically. 2. [write default] : initialize the register of the ak4641 3. [all read] : read all registers of the ak4641. 4. [all write] : write all registers that is currently displayed 5. [function1] : dialog to write data by keyboard operation. 6. [function2] : dialog to evaluate ipga and attl/attr. 7. [function3] : the sequence of register setting can be set and executed. 8. [function4] : the sequence that is created on [function3] can be assigned to buttons and executed. 9. [function5] : the register setting that is created by [save] function on main window can be assigned to buttons and executed. 10.[write] : dialog to write data by mouse operation. 11.[read] : read data by mouse operation. 12.[save] : save the current register setting. 13.[open] : write the save values to all register. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
asahi kasei [akd4641en-a] 2006/03 - 15 - ? explanation of each dialog 1. [function1 dialog] : dialog to write data by keyboard operation address box: input register address in 2 figures of hexadecimal. data box: input register data in 2 figures of hexadecimal. if you want to write the input data to ak4641, click ?ok? button. if not, click ?cancel? button. 2. [function2 dialog] : dialog to evaluate ipga and attl/attr this dialog corresponds to only addr=0bh and 0ch, 0dh. address box: input register address in 2 figures of hexadecimal. start data box: input start data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to ak4641 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to ak4641, click ?ok? button. if not, click ?cancel? button. 3. [write dialog] : dialog to write data by mouse operation there are dialogs corresponding to each register. click the ?write? button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to ak4641, click ?ok? button. if not, click ?cancel? button. 4.[save] and [open] 4-1. [save] save the current register setting data. the extension of file name is ?akr?. (operation flow) (1) click [save] button. (2) set the file name and push [save] button. the extension of file name is ?akr?. 4 -2. [open] the register setting data saved by [save] is written to ak4643. the file type is the same as [save]. (operation flow) (1) click [open] button. (2) select the file (*.akr) and click [open] button.
asahi kasei [akd4641en-a] 2006/03 - 16 - 5.[function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. (2) set the control sequence. set the address, data and interval time. set ?-1? to the address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 1. window of [f3]
asahi kasei [akd4641en-a] 2006/03 - 17 - 6. [function4 dialog] the sequence that is created on [function3] can be assigned to buttons and executed. when [f4] button is clicked, the window as shown in figure2 opens. figure 2. [f4] window
asahi kasei [akd4641en-a] 2006/03 - 18 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks). the sequence file name is displayed as shown in figure 3. figure 3. [f4] window(2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] bu ttons on right side [save] : the sequence file names can assi gn be saved. the file name is *.ak4. [open] : the sequence file names assign that are saved in *.ak4 are loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files need to be in same folder used by [save] and [open] function on right side. (3) when the sequence is changed in [function3], the file should be loaded again in order to reflect the change.
asahi kasei [akd4641en-a] 2006/03 - 19 - 7.[function5 dialog] the register setting that is created by [save] function on main window can be assigned to buttons and executed. when [f5] button is clicked, the following window as shown in figure 4 opens. figure 4. [f5] window 7-1. [open] buttons on left side and [write] button ( 1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 5. (2) click [write] button, then the register setting is executed.
asahi kasei [akd4641en-a] 2006/03 - 20 - figure 5. [f5] windows(2) 7-2. [save] and [open] buttons on right side [save] : the register setting file names assign can be saved. the file name is *.ak5 . [open] : the register setting file names assign that are saved in *.ak5 are loaded. 7-3. note (1) all files need to be in same folder used by [save] and [open] function on right side. (2) when the register setting is changed by [save] button in main window, the file should be loaded again in order to reflect the change.
asahi kasei [akd4641en-a] 2006/03 - 21 - measurement result 1. 16bit stereo codec [measurement condition] ? measurement unit : audio precision, system two ? mclk : 256fs ? bick : 64fs ? fs : 44.1khz ? bit : 16bit ? power supply : avdd=bvdd=dvdd=3.3v ? measurement filter : 20hz 20khz ? temperature : room [measurement results] 1.adc (int) characteristics (mic gain = +20db, ipga = 0db, alc1 = off, mic ? ipga ? adc) [db] thd+n 20khzlpf (-1db) 83.3 dr 20khzlpf + a-weighted 86.1 s/n 20khzlpf + a-weighted 86.1 2.adc (ext) characteristics (mic gain = +20db, ipga = 0db, alc1 = off, ext ? ipga ? adc) [db] thd+n 20khzlpf (-1db) 83.3 dr 20khzlpf + a-weighted 86.1 s/n 20khzlpf + a-weighted 86.1 3. adc (auxin+ / auxin-) characteristics ( micad =0, auxin+/auxin- ? adc) [db] thd+n 20khzlpf (-1db) 87.6 dr 20khzlpf + a-weighted 91.1 s/n 20khzlpf + a-weighted 91.1 4. dac (lout/rout) characteristics (r l =10k ? , dac ? lout/rout) l[db] r[db] thd+n 20khzlpf (-3db) 86.4 86.4 dr 20khzlpf + a-weighted 89.4 89.5 s/n 20khzlpf + a-weighted 90.7 91.0 5. dac (mout+ / mout-) characteristics (r l =20k ? , dac ? mout+ / mout-) mogn=0[db] mogn=1[db] thd+n 20khzlpf (-3db) 87.7 74.0 dr 20khzlpf + a-weig hted 90.9 76.8 s/n 20khzlpf + a-weighted 93.0 77.0 6. dac (mout2) characteristics (r l =10k ? , dac ? mix ? mout2) [db] thd+n 20khzlpf (-3db) 87.9 dr 20khzlpf + a- weighted 90.7 s/n 20khzlpf + a-weighted 92.7
asahi kasei [akd4641en-a] 2006/03 - 22 - 2. 16bit mono codec [measurement condition] ? measurement unit : rohde & schwarz, upd05 ? bbick : 32fs ? fs : 8khz ? bit : 16bit ? power supply : avdd=bvdd=dvdd=3.3v ? measurement filter : 20hz 4khz ? temperature : room [measurement results] 1. adc (auxin) characteristics ( micad =0, auxin ? mixer ? adc, aux volume = 0db) [db] thd+n 20khzlpf (-1db) 78.5 dr 20khzlpf + a-weighted 88.7 s/n 20khzlpf + a-weighted 88.9 2. dac (mout) characteristics (r l =20k ? , dac ? mout, att = 0db) [db] thd+n 20khzlpf (-0db) 78.9 dr 20khzlpf + a- weighted 91.4 s/n 20khzlpf + a-weighted 92.0 3. loop-back (auxin ? adc ? dac ? mout) [db] thd+n 20khzlpf (-3db) 76.7 dr 20khzlpf + a- weighted 87.9 s/n 20khzlpf + a-weighted 88.0
asahi kasei [akd4641en-a] 2006/03 - 23 - 3. 16bit stereo codec plot data 3-1. adc (mic ? ipga ? adc) plot data akm ak4641 adc(int) thd+n vs. input level vdd=3.3v, fs=44.1khz, fin=1khz -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b f s -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr figure 1. thd+n vs. input level akm ak4641 adc(int) thd+n vs. input frequency vdd=3.3v, fs=44.1khz, input=-1db -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 2. thd+n vs. input frequency
asahi kasei [akd4641en-a] 2006/03 - 24 - akm ak4641 adc (int) linearity vdd=3.3v, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 3. linearity akm ak4641 adc (int) frequency response vdd=3.3v, fs=44.1khz, input=-1db 20 20k 50 100 200 500 1k 2k 5k 10k hz -5 -0 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 d b f s figure 4. frequency response
asahi kasei [akd4641en-a] 2006/03 - 25 - akm ak4641 adc(int) fft plot vdd=3.3v, fs=44.1khz, fin=1khz, input=-1db -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 5. fft plot ( input level=-1dbfs) akm ak4641 adc(int) fft plot vdd=3.3v, fs=44.1khz, fin=1khz, input=-60db -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 6. fft plot ( input level=-60dbfs )
asahi kasei [akd4641en-a] 2006/03 - 26 - akm ak4641 adc(int) fft plot vdd=3.3v, fs=44.1khz, input=no signal -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 7. fft plot ( no signal )
asahi kasei [akd4641en-a] 2006/03 - 27 - 3-2. dac ( dac ? mono out ) plot data akm ak4641 dac(lout/rout) thd+n vs. input level vdd=3.3v, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b r a figure 8. thd+n vs. input level akm ak4641 dac(lout/rout) thd+n vs. input frequency vdd=3.3v, fs=44.1khz, input level=-3db 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b r a figure 9. thd+n vs. input frequency
asahi kasei [akd4641en-a] 2006/03 - 28 - akm ak4641 dac(lout/rout) linearity vdd=3.3v, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 10 linearity akm ak4641 dac (lout/rout) frequency response vdd=3.3v, fs=44.1khz, input=-0db 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz -0.5 +0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 d b r a figure 11. frequency response
asahi kasei [akd4641en-a] 2006/03 - 29 - akm ak4641 dac(lout/rout) fft plot vdd=3.3v, fs=44.1khz, fin=1khz, input level=-3db 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 12. fft plot ( input level=-3dbfs ) akm ak4641 dac(lout/rout) fft plot vdd=3.3v, fs=44.1khz, fin=1khz, input=-60db 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 13. fft plot ( input level=-60.0dbfs )
asahi kasei [akd4641en-a] 2006/03 - 30 - akm ak4641 dac(lout/rout) fft plot vdd=3.3v, fs=44.1khz, input=no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 14. fft plot ( no signal ) akm ak4641 dac(lout/rout) fft plot vdd=3.3v, fs=44.1khz, input = no signal 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 15. out-of-band noise
asahi kasei [akd4641en-a] 2006/03 - 31 - akm ak4641 dac (lout/rout) crosstalk vdd=3.3v, fs=44.1khz, input=-0db 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b figure 16. crosstalk plot
asahi kasei [akd4641en-a] 2006/03 - 32 - 4. 16bit mono codec plot data 4-1. adc (auxin ? mixer ? adc) plot data figure 17. thd+n vs. input level figure 18. thd+n vs. input frequency
asahi kasei [akd4641en-a] 2006/03 - 33 - figure 19. linearity figure 20. frequency response
asahi kasei [akd4641en-a] 2006/03 - 34 - figure 21. fft plot ( input level=-1dbfs) figure 22. fft plot ( input level=-60dbfs )
asahi kasei [akd4641en-a] 2006/03 - 35 - figure 23. fft plot ( no signal )
asahi kasei [akd4641en-a] 2006/03 - 36 - 4-2. dac (dac ? mono out ) plot data figure 24. thd+n vs. input level figure 25. thd+n vs. input frequency
asahi kasei [akd4641en-a] 2006/03 - 37 - figure 26 linearity figure 27. frequency response
asahi kasei [akd4641en-a] 2006/03 - 38 - figure 28. fft plot ( input level=-0dbfs ) figure 29. fft plot ( input level=-60.0dbfs )
asahi kasei [akd4641en-a] 2006/03 - 39 - figure 30. fft plot ( no signal )
asahi kasei [akd4641en-a] 2006/03 - 40 - revision history date (yy/mm/dd) manual revision board revision reason contents 05/11/29 km082000 0 first edition 06/03/13 km082001 1 update change of a figure & circuit important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a reg(+5v) avdd bvdd dvdd vcc(d3.3v) ext int auxin+ auxin- mout+ mout- lout 4641_bick 4641_lrck 4641_sdti sda scl tst1 4641_sdto dvdd1 dvdd1 4641_bsdto bsync mout2 rout 4641_pdn 4641_mcki bsdti bbick reg reg avdd0 bvdd0 tst2 bvdd0 avdd0 d3.3v dvdd0 dvdd0 title size document number rev date: sheet of ak4641 a akd4641 a3 16 friday, november 25, 2005 title size document number rev date: sheet of ak4641 a akd4641 a3 16 friday, november 25, 2005 title size document number rev date: sheet of ak4641 a akd4641 a3 16 friday, november 25, 2005 dgnd agnd agnd avdd agnd reg avdd agnd bvdd bvdd agnd dvdd vcc dgnd dvdd r5 51 r5 51 1 2 l4 short l4 short 10 11 12 13 14 15 16 17 18 cn4 cn4 + c4 1u + c4 1u + c8 2.2u + c8 2.2u r15 51 r15 51 in out gnd t1 ta48m33f t1 ta48m33f jp3 avdd_sel jp3 avdd_sel 1 2 l2 short l2 short + c3 47u + c3 47u r14 51 r14 51 jp1 gnd jp1 gnd + c16 10u + c16 10u r10 51 r10 51 r16 (short) r16 (short) + c10 10u + c10 10u r1 2.2k r1 2.2k + c5 1u + c5 1u mpe 1 mpi 2 int 3 vcom 4 avss 5 avdd 6 bvdd 7 bvss 8 vcoc 9 pdn 10 tst1 11 scl 12 sda 13 sdti 14 sdto 15 lrck 16 bick 17 mclk 18 dvdd 19 dvss 20 bsdti 21 bsdto 22 bsync 23 bbick 24 tst2 25 mout2 26 rout 27 lout 28 mout- 29 mout+ 30 auxin- 31 auxin+ 32 ain 33 micout 34 mdt 35 ext 36 u1 ak4641 u1 ak4641 jp4 bvdd_sel jp4 bvdd_sel r12 51 r12 51 r4 51 r4 51 19 20 21 22 23 24 25 26 27 cn3 cn3 1 2 l1 short l1 short + c13 10u + c13 10u 1 2 3 4 5 6 7 8 9 cn2 cn2 c1 0.1u c1 0.1u jp2 d3.3v_sel jp2 d3.3v_sel r2 2.2k r2 2.2k c11 0.1u c11 0.1u + c12 47u + c12 47u c15 0.1u c15 0.1u r6 51 r6 51 + c19 47u + c19 47u r7 5.1k r7 5.1k + c18 47u + c18 47u c9 0.1u c9 0.1u 28 29 30 31 32 33 34 35 36 cn1 cn1 1 2 l3 short l3 short r13 51 r13 51 r3 51 r3 51 + c7 1u + c7 1u r11 51 r11 51 + c6 47u + c6 47u r8 51 r8 51 jp5 dvdd_sel jp5 dvdd_sel r9 51 r9 51 c17 470n c17 470n c14 0.1u c14 0.1u c2 0.1u c2 0.1u
a a b b c c d d e e e e d d c c b b a a h/svdd int ext mout2 mout+ mout- auxin+ auxin- lout rout h/svdd h/svdd h/svdd h/svdd title size document number rev date: sheet of input/output a akd4641 a3 26 friday, november 25, 2005 title size document number rev date: sheet of input/output a akd4641 a3 26 friday, november 25, 2005 title size document number rev date: sheet of input/output a akd4641 a3 26 friday, november 25, 2005 int ext mout- mout+ rca rca rca rca rca 020s16 spk1 l r lout hp hp rout mout2 spk rca jp11 mic jp11 mic r25 20k r25 20k r37 20k r37 20k jp8 shdn_l jp8 shdn_l jp7 rout/hp_sel jp7 rout/hp_sel + c31 22u + c31 22u jp9 shdn_r jp9 shdn_r + c23 22u + c23 22u + c20 1u + c20 1u r34 20k r34 20k r24 (short) r24 (short) r41 100 r41 100 r17 10k r17 10k r36 20k r36 20k + c29 1u + c29 1u jp10 shdn jp10 shdn jp15 shdn_spk jp15 shdn_spk + c24 2.2u + c24 2.2u r29 47k r29 47k r32 10k r32 10k 2 2 3 3 1 1 j9 mout j9 mout r19 220 r19 220 + c32 100p + c32 100p j1 lout j1 lout j8 mout+ j8 mout+ + c34 22u + c34 22u jp12 mout2/spk_sel jp12 mout2/spk_sel 1 2 l5 (short) l5 (short) r26 20k r26 20k pvss 6 c1p 3 pvdd 2 pgnd 4 outl 8 outr 11 shdnr 12 inl 10 c1n 5 shdnl 1 svdd 9 inr 13 svss 7 sgnd 14 u2 max4410 u2 max4410 r42 10k r42 10k r20 10k r20 10k r40 100 r40 100 r35 10k r35 10k + c25 2.2u + c25 2.2u + c27 1u + c27 1u r31 220 r31 220 jp13mout+/-_sel jp13mout+/-_sel r30 47k r30 47k 1 2 + c28 47u + c28 47u j2 hp j2 hp jp6 lout/hp_sel jp6 lout/hp_sel + c30 22u + c30 22u j6 auxin- j6 auxin- j5 auxin+ j5 auxin+ j4 mic j4 mic jp16 diff2 jp16 diff2 r23 (short) r23 (short) + c21 22u + c21 22u r21 10k r21 10k r28 10k r28 10k r22 10k r22 10k j7 mout2 j7 mout2 + c26 2.2u + c26 2.2u 1 2 cn5 cn5 r27 220 r27 220 r33 220 r33 220 shutdown 1 bypass 2 +in 3 vo1 5 -in 4 vo2 8 vdd 6 gnd 7 u3 lm4889 u3 lm4889 r38 (short) r38 (short) r39 10k r39 10k r18 10k r18 10k + c36 1u + c36 1u + c35 1u + c35 1u + c22 1u + c22 1u + c33 0.47u + c33 0.47u j3 rout j3 rout jp14 diff1 jp14 diff1
a a b b c c d d e e e e d d c c b b a a ext_bsync ext_bbick mclk_256fs d3.3v port_bsync title size document number rev date: sheet of clock_bth a akd4641 a3 3 6 wednesday, july 23, 2003 title size document number rev date: sheet of clock_bth a akd4641 a3 3 6 wednesday, july 23, 2003 title size document number rev date: sheet of clock_bth a akd4641 a3 3 6 wednesday, july 23, 2003 128fs 64fs 32fs 2fs ext 512fs 1fs ext ext i2s short clk 256fs clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 u5 74vhc4040 u5 74vhc4040 1 2 3 u6a 74ac08 u6a 74ac08 jp21 bsync_sel2 jp21 bsync_sel2 r44 51 r44 51 j10 bbick j10 bbick jp19 clk_sel jp19 clk_sel d 2 clk 3 q 5 q 6 pr 4 cl 1 u7a 74ac74 u7a 74ac74 r45 51 r45 51 1 2 u8a 74ac04 u8a 74ac04 jp18 bbick_sel jp18 bbick_sel jp22 ext1 jp22 ext1 r43 1m r43 1m 1 2 u4a 74hcu04 u4a 74hcu04 1 2 x1 4.096mhz x1 4.096mhz 3 4 u4b 74hcu04 u4b 74hcu04 jp17 xte jp17 xte c38 15p c38 15p d 12 clk 11 q 9 q 8 pr 10 cl 13 u7b 74ac74 u7b 74ac74 c37 15p c37 15p jp23 ext2 jp23 ext2 j11 bsync j11 bsync jp20 bsync_sel1 jp20 bsync_sel1
a a b b c c d d e e e e d d c c b b a a 4641_lrck 4641_sdti dir_bick 4641_mcki dir_mclk1 4641_bick bsdto tst2n tst1 4641_pdn scl sda dir_lrck dir_mclk2 4641_sdto sdto dir_sdti d3.3v d3.3v d3.3v d3.3v d3.3v d3.3v title size document number rev date: sheet of logic_audio a akd4641 a3 56 wednesday, july 23, 2003 title size document number rev date: sheet of logic_audio a akd4641 a3 56 wednesday, july 23, 2003 title size document number rev date: sheet of logic_audio a akd4641 a3 56 wednesday, july 23, 2003 lrck loop dir mclk vcc sdti bick scl cdto sda csn lh dir port dir port inv thr port dir dir port mcko1 mcko2 r61 1.8k r61 1.8k 5 6 u9c 74hc14 u9c 74hc14 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u13 74hc541 u13 74hc541 1 2 3 4 5 6 7 8 9 10 port3 audio i/f port3 audio i/f 1 2 u16a 74lvc07 u16a 74lvc07 r57 470 r57 470 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u12 74lvc541 u12 74lvc541 jp28 bick_inv jp28 bick_inv r60 10k r60 10k r56 10k r56 10k c55 0.1u c55 0.1u 1 2 u19a 74hc14 u19a 74hc14 2 1 3 sw2 pdn sw2 pdn jp32 sdti1 jp32 sdti1 r59 470 r59 470 1 2 3 4 5 6 7 8 9 10 port4 ctrl port4 ctrl jp30 bick2 jp30 bick2 r52 10k r52 10k c54 0.1u c54 0.1u jp27 bick1 jp27 bick1 1a 2 1b 3 2a 5 2b 6 3a 11 3b 10 4a 14 4b 13 a/b 1 g 15 1y 4 2y 7 3y 9 4y 12 u15 74lvc157 u15 74lvc157 r53 100k r53 100k r54 10k r54 10k r62 10k r62 10k jp31 lrck2 jp31 lrck2 jp29 lrck1 jp29 lrck1 c53 0.1u c53 0.1u 9 8 u9d 74hc14 u9d 74hc14 r55 470 r55 470 r58 10k r58 10k jp33 sdti2 jp33 sdti2 jp26 mclk_sel jp26 mclk_sel 2 1 d2 hsu119 d2 hsu119 jp34 bsdto jp34 bsdto
a a b b c c d d e e e e d d c c b b a a ext_bbick bsdti bbick ext_bsync bsync bsdto 4641_bsdto mclk_256fs d3.3v d3.3v d3.3v d3.3v port_bsync title size document number rev date: sheet of logic_bth a akd4641 a3 66 wednesday, july 23, 2003 title size document number rev date: sheet of logic_bth a akd4641 a3 66 wednesday, july 23, 2003 title size document number rev date: sheet of logic_bth a akd4641 a3 66 wednesday, july 23, 2003 mclk bbick bsync bsdti vcc thr int inv port port int port port int int for 74ac02,74ac74,74hc04,74hc14,74hc14,74ac4040,74hcu04,74lvc07,74lvc157,74ac04 port loop 11 10 u16e 74lvc07 u16e 74lvc07 jp39 bbick_inv jp39 bbick_inv c56 0.1u c56 0.1u 12 13 11 u6d 74ac08 u6d 74ac08 c59 0.1u c59 0.1u 11 10 u9e 74hc14 u9e 74hc14 5 6 u11c 74hc04 u11c 74hc04 c66 0.1u c66 0.1u 13 12 u9f 74hc14 u9f 74hc14 c58 0.1u c58 0.1u a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u18 74hc541 u18 74hc541 jp36 bsync2 jp36 bsync2 + c68 47u + c68 47u 4 5 6 u6b 74ac08 u6b 74ac08 5 6 u16c 74lvc07 u16c 74lvc07 c57 0.1u c57 0.1u jp40 bsync1 jp40 bsync1 jp35 bbick2 jp35 bbick2 13 12 u8f 74ac04 u8f 74ac04 9 8 u4d 74hcu04 u4d 74hcu04 11 10 u11e 74hc04 u11e 74hc04 3 4 u19b 74hc14 u19b 74hc14 13 12 u16f 74lvc07 u16f 74lvc07 c65 0.1u c65 0.1u 9 8 u11d 74hc04 u11d 74hc04 5 6 u19c 74hc14 u19c 74hc14 c63 0.1u c63 0.1u a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u17 74lvc541 u17 74lvc541 13 12 u19f 74hc14 u19f 74hc14 13 12 u11f 74hc04 u11f 74hc04 11 10 u4e 74hcu04 u4e 74hcu04 9 8 u16d 74lvc07 u16d 74lvc07 9 10 8 u6c 74ac08 u6c 74ac08 9 8 u8d 74ac04 u8d 74ac04 r64 10k r64 10k 11 10 u19e 74hc14 u19e 74hc14 c60 0.1u c60 0.1u r63 100k r63 100k 5 6 u8c 74ac04 u8c 74ac04 jp38 bbick1 jp38 bbick1 9 8 u19d 74hc14 u19d 74hc14 jp37 sdti jp37 sdti c62 0.1u c62 0.1u 1 2 3 4 5 6 7 8 9 10 port5 bth i/f port5 bth i/f 3 4 u16b 74lvc07 u16b 74lvc07 c64 0.1u c64 0.1u c61 0.1u c61 0.1u c67 0.1u c67 0.1u 13 12 u4f 74hcu04 u4f 74hcu04 3 4 u8b 74ac04 u8b 74ac04 11 10 u8e 74ac04 u8e 74ac04 5 6 u4c 74hcu04 u4c 74hcu04
a a b b c c d d e e e e d d c c b b a a sdto dir_sdti dir_bick dir_lrck dir_mclk1 cm1 cm0 cm0 d3.3v d3.3v ocks1 tst2 cm1 ocks1 dir_mclk2 d3.3v d3.3v tst2n d3.3v d3.3v d3.3v title size document number rev date: sheet of dir/dit a akd4641 a3 46 wednesday, july 23, 2003 title size document number rev date: sheet of dir/dit a akd4641 a3 46 wednesday, july 23, 2003 title size document number rev date: sheet of dir/dit a akd4641 a3 46 wednesday, july 23, 2003 h l dif0 dif2 cm0 ocks1 tst2 cm1 c41 0.1u c41 0.1u gnd 1 vcc 2 in 3 port2 totx141 port2 totx141 c45 0.47u c45 0.47u 3 4 u9b 74hc14 u9b 74hc14 1 2 u11a 74hc04 u11a 74hc04 r49 1k r49 1k r46 10k r46 10k j12 ext j12 ext r50 51 r50 51 + c50 10u + c50 10u c47 10p c47 10p c44 0.1u c44 0.1u 2 1 led1 erf led1 erf out 1 vcc 3 gnd 2 port1 torx141 port1 torx141 7 6 5 4 3 2 1 rp1 47k rp1 47k c48 0.1u c48 0.1u c49 0.1u c49 0.1u 1 2 u9a 74hc14 u9a 74hc14 c39 0.1u c39 0.1u + c42 10u + c42 10u c43 0.1u c43 0.1u 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sw3 mode sw3 mode 1 2 x2 11.2896mhz x2 11.2896mhz jp25 ext jp25 ext jp24 xti jp24 xti 3 4 u11b 74hc04 u11b 74hc04 c52 0.1u c52 0.1u c46 10p c46 10p r47 470 r47 470 2 1 3 sw1 dir sw1 dir c40 0.1u c40 0.1u ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 u10 ak4114 u10 ak4114 2 1 d1 hsu119 d1 hsu119 + c51 10u + c51 10u r51 51 r51 51 r48 18k r48 18k 1 2 l6 (short) l6 (short)
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